In distributed processing systems, multiple processors communicate with each other and with memory devices to perform a shared computation. Because the types of computations involved are generally very complex or require a great deal of processing power, this type of communication often must be very high speed.
High-performance computing (“HPC”) systems further increase speed by using specialized hardware that is not generally available commercially off-the-shelf for use in, for example, desktop or server computers. This specialized hardware often includes a plurality of computing nodes having customized application-specific integrated circuits (“ASICs”) with a number of communications channels for communicating with other ASICS on other nodes (and components on the same node). Such hardware also includes the processors, memory, and other specialized hardware unique to implement a tightly-coupled HPC system. HPC systems thus often divide execution of complex computations across multiple of these interconnected nodes.
In dividing a computational task, the nodes often are allocated a prescribed power range in which they can operate. This power range typically is set by some central controller that allocates a common power range for all relevant nodes. Such a system, however, does not account for differing power requirements of different nodes at different times. Accordingly, prior art HPC systems known to the inventors taking such an approach can suffer from inefficiencies, latencies, and jitter.